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fully integrated afe for adsl overall 12 bit resolution, 1.1mhz signal bandwidth 8.8ms/s adc 8.8ms/s dac thd: -60db @full scale 4-bit digital interface to/from the dmt modem 1v full scale input differential analog i/o accurate continuous-time channel filtering 3rd & 4th order tunable continuous time lp filters 0.5 watt at 3.3v 0.5 m m hcmos5 la technology 64 pin tqfp package description STLC60134S is the analog front end of the stmicroelectronics tosca ? adsl chipset and when coupled with stlc60135 (dtm modem) al- lows to get a t1.413 issue 2 compliant solution. the STLC60134S analog front end handles 2 transmission channels on a balanced 2 wire inter- connection; a 16 to 640kbit/s upstream channel and a 1.536 to 8.192mbit/s downstream channel. a 256 carrier dmt coding (frequency spacing 4.3125khz) transforms the downstream channel to a 1mhz bandwidth analog signal (tones 32- 255) and the upstream channel (tones 8-31) to a 100khz bandwidth signal on the line. this asymmetrical data transmission system uses high resolution, high speed analog to digital and digital to analog conversion and high order ana- log filtering to reduce the echo and noise in both august 1999 ? 1.1mhz hc2 1.1mhz hc1 138khz sc2 r-mos-c tuning i/v-ref xtal-driver vcxo dac + + - - + + - - adc error correction analog loop digital loop mux dac mux 13 bits 4 bits 12 bits 4 bits digital if g=-15...0db step=1db g=0..31db step=1db agctx agcrx txp txn rxp(0:1) rxn(0:1) d99tl453 figure 1. block diagram tqfp64 ordering number: STLC60134S STLC60134S tosca ? integrated adsl cmos analog front-end circuit 1/22
the atu-c/atu-r receivers and transmitters. ex- ternal low noise driver and input stage used with STLC60134S guarantee low noise performances. the STLC60134S chip can be used at atu-c and atu-r ends (behaviour set by ltnt pin). the selection consists mainly of a filter inter- change between the rx and tx path. the filters (with a programmable cutoff frequency) use auto- matic continuous time tuning to avoid time vary- ing phase characteristic which can be of dramatic consequence for dmt modem. it requires few ex- ternal components, uses a 3.3v supply (a sepa- rate 3.0v supply of the digital part is possible) and is packaged in a 64-pin tqfp in order to re- duce pcb area. the receiver (rx) part the dmt signal coming from the line to the STLC60134S is first filtered by the two following external filters: pots hp filter: attenuation of speech and pots signalling channel filter: attenuation of echo signal to improve rx dynamic an analog multiplexer allows the selection be- tween two input ports which can be used to select an attenuated (0, 10db for ex.) version of the sig- nal in case of short loop or large echo. the sig- nal is amplified by a low noise gain stage (0- 31db) then low-pass filtered to avoid anti-aliasing and to ease further digital processing by remov- ing unwanted high frequency out-of-band noise. a 12-bit a/d converter samples the data at 8.832ms/s (or 4.416ms/s in alternative mode), transforms the signal into a digital representation and sends it to the dmt signal processor via the digital interface. the transmitter (tx) part the 12-bit data words at 8.832ms/s (or 4.416ms/s) coming from the dmt signal proces- sor through the digital interface are transformed by d/a converter into a analog signal. this signal is then filtered to decrease dmt side- lobes level and meet the ansi transmitter spec- tral response but also to reduce the out-of-band noise (which can be echoed to the rx path) to an acceptable level. the pre-driver buffers the signal for the external line driver and in case of short loop provide attenuation (-15...0db). the vcxo part the vcxo is divided in a xtal driver and a aux- iliary 8 bits dac for timing recovery. the xtal driver is able to operate at 35.328mhz and provides an amplitude regulation mechanism to avoid temperature / supply / technology de- pendent frequency pulling. the dac which is driven by the ctrlin pin pro- vides a current output with 8-bit resolution and can be used to tune the xtal frequency with the help of external components. a time constant be- tween dac input and vcxo output can be intro- duced (via the ctlin interface) and programmed with the help of an external capacitor (on vcoc pin). see chapter 'vcxo' for the external circuit re- lated to the vcxo . the digital interface part the digital part of the STLC60134S can be di- vided in 3 sections: the data interface converts the multiplexed data from/to the dmt signal processor into valid representation for the tx dac and rx adc. it performs also the error correction mechanism needed at the (redundant) adc output. the control interface allows the board proces- sor to configure the STLC60134S paths (rx/tx gains, filter band, ...) or settings (osr, vcodac enable, digital / analog loopback,...). the test interface to enable digital (full scan, nandtree, loop backs, functional,...) or analog (tin, tout assignation) tests to be per- formed. dmt signal a dmt signal is basically the sum of n inde- pendently qam modulated signals, each carried over a distinct carrier. the frequency separation of each carrier is 4.3125khz with a total number of 256 carriers (ansi). for n large, the signal can be modelled by a gaussian process with a certain amplitude probability density function. since the maximum amplitude is expected to arise very rarely, we decide to clip the signal and to trade- off the resulting snr loss against ad/da dy- namic. a clipping factor (vpeak/vrms = ocrest fac- toro) of 5 will be used resulting in a maximum snr of 75db. adsl dmt signals are nominally sent at -40dbm/hz 3db (-3.65dbm/carrier) with a maximal power of 100mw for down link transmitter and 15.7mw for uplink transmitter. dmt symbols are transmitted without 'window- ing' causing sin (x)/x like sidelobes. for spectral response shaping, the 1st sidelobe level is as- sumed to be 13db under the carrier level with an attenuation of -20db/dec. the minimum snr + d neede d for dmt carrier demodulation is about (3 ? n + 20) db with a minimum of 38db were n is the constellation size of a carrier (in bits). STLC60134S 2/22
maximum / minimum signal levels the following table gives the transmitted and re- ceived signal levels for both atu-r and atu-c sides. all the levels are referred to the line volt- ages (i.e. after hybrid and transformers in tx di- rection, before hybrid and transformer in rx di- rection). note that signal amplitudes shown below are for illustration purpose and depending on the trans- mit power and line impedance signal amplitudes can differ from these values. the reference line impedance for all power calcu- lations is 100 w . package the STLC60134S is packaged in a 64-pin tqfp package (body size 10x10mm, pitch 0.5mm). table 1. target signal levels (on the line). parameter atu - c atu - r rx tx rx tx max level 839 mvpdif 15.8 vpdif 3.95 vpdif 3.4 vpdif max rms level 168 mvrms 3.16 vrms 791 mvrms 671 mvrms min level 54 mvpdif 3.95 vpdif 42 mvpdif 839 mvpdif min rms level 11 mvrms 791 mvrms 8 mvrms 168 mvrms table 2. total signal level (on the line). parameter atu - c atu - r rx tx rx tx max level for receiver 4 vpdif (long line) 4.2 vpdif (short line) 1 2 3 5 6 4 7 8 9 10 27 11 28 29 30 31 32 59 58 57 56 54 55 53 52 51 50 49 43 42 41 39 38 40 48 47 46 44 45 nu0 nu1 nu2 tx0 tx1 nu3 clwd clnib clkm ctrlin dvss1 gp0 avss3 vrap vref avdd3 vran avdd4 nc0 nc1 txp txn xtali avdd1 res vcxo avdd2 ivco iref avss2 avss6 rxip1 rxin1 gp2 avdd6 avdd5 res agnd res rxip0 rxin0 gc1 vcoc gc0 d98tl355mod 22 23 24 25 26 60 xtalo 61 avss1 62 dvss2 63 tx3 64 tx2 dvdd2 pdown ltnt resetn res 17 18 19 20 21 37 36 34 33 35 res res avss4 gp1 avss5 12 13 14 15 16 dvdd1 rx0 rx1 rx3 rx2 figure 2. pin connection STLC60134S 3/22
table 3. pin functions. n. name function pcb connection supply analog interface 24 vrap positive voltage reference adc decoupling network avdd3 25 vref ground reference adc decoupling network avdd3 26 vran negative voltage reference adc decoupling network avdd3 31 txp pre driver output line driver input avdd4 32 txn pre driver output line driver input avdd4 38 agnd virtual analog ground (avdd/2 = 1.65v) decoupling network avdd5 44 vcoc vcodac time constant capacitor vcodac cap. avdd5 45 gc0 external gain control output lsb avdd5 46 gc1 external gain control output msb avdd5 47 rxn0 analog receive negative input gain 0 echo filter output avdd5 48 rxp0 analog receive positive input gain 0 echo filter output avdd5 49 rxn1 analog receive negative input gain 1 (most sensitive input) echo filter output avdd5 50 rxp1 analog receive positive input gain 1 (most sensitive input) echo filter output avdd5 53 iref current reference tx dac/dace decoupling network avdd2 55 ivco current reference vco dac vco bias network avdd1 56 vcxo vxco control current vcxo filter avdd1 59 xtali xtal oscillator input pin crystal + varicap avdd1 60 xtalo xtal oscillator output pin crystal + varicap avdd1 digital interface 1 tx1 digital transmit input, parallel data dvdd2 2 tx0 digital transmit input, parallel data dvdd2 7 ctrlin serial data input (settings) async interface dvdd2 9 clkm master clock output, f = 35.328mhz load = cl<30pf dvdd2 10 clnib nibble clock output, f = 17. 664mhz (osr = 2) or ground (osr = 4) load = cl<30pf dvdd2 11 clwd word clock output, f = 8.832/4.416mhz load = cl<30pf dvdd2 12 rx3 digital receive output, parallel data load = cl<30pf dvdd2 13 rx2 digital receive output, parallel data load = cl<30pf dvdd2 14 rx1 digital receive output, parallel data load = cl<30pf dvdd2 15 rx0 digital receive output, parallel data load = cl<30pf dvdd2 18 pdown power down select, o1o = power down power down input dvdd2 19 ltnt atu-r / atu-c select pin 1 , atu-r = 0 /atu-c = 1 / test mode msb vdd in atu-c mode dvdd2 20 resetn reset pin (active low) rc- reset dvdd2 22 gp0 general purpose output 0 (on avdd 1) echo filter output avdd 33 gp1 general purpose output 1 (on avdd 1) echo filter output avdd 43 gp2 general purpose output 2 (on avdd 1) echo filter output avdd 63 tx3 digital transmit input, parallel data load = cl<30pf dvdd2 64 tx2 digital transmit input, parallel data load = cl<30pf dvdd2 21 res reserved must be connected to dvss (input) 36, 37, 39, 40, 57 res reserved must be connected to avss (input) supply voltages 8 dvss1 dvss 16 dvdd1 digital i/o supply voltage dvdd 17 dvdd2 digital internal supply voltage dvdd 23 avss3 avss 27 avdd3 adc supply voltage avdd STLC60134S 4/22
atu-c end: block diagram the transformer at atu-c side has 1:2 ratio. the termination resistors are 12.5 w in case of 100 w lines. the hybrid bridge resistors should be < 2.5k w for low-noise. an hp filter must be used on the tx path to re- duce dmt sidelobes and out of band noise influ- ence on the receiver. on the rx path, a lp filter must be used in order to reduce the echo signal level and to avoid saturation of the input stage of the receiver. the pots filter is used in both directions to re- duce crosstalk between STLC60134S signals and pots speech and signalling. 4.7 m h l1 10 m f 100nf analog vdd avdd (each pin must have its own capacitor) 10 m f 100nf 10 m f 100nf 10 m f vrap pin vran pin 10 m f 100nf vref pin 10 m f 100nf agnd pin 10 m f 100nf iref pin vcoc pin d98tl356 100nf figure 3. grounding and decoupling networks. table 3. pin functions (continued) 28 avdd4 tx pre - drivers supply avdd 34 avss4 avss 35 avss5 avss 41 avdd5 ct filter supply avdd 42 avdd6 lna supply avdd 51 avss6 avss 52 avss2 avss 54 avdd2 dac and support circuit avdd 58 avdd1 xtal oscillator supply voltage avdd 61 avss1 avss 62 dvss2 dvss spares 3 nu3 not used inputs dvss 4 nu2 not used inputs dvss 5 nu1 not used inputs dvss 6 nu0 not used inputs dvss 29 nc0 30 nc1 1 lt ? aut-c; nt ? atu-r STLC60134S 5/22
atu-r end: block diagram the atu-r side block diagram is equal to the atu-c side block diagram with the following dif- ferences: - the transformer ratio is 1:1 - termination resistors are 50 w for 100 w lines. an lp filter may be used on the tx path to re- duce dmt sidelobes and out of band noise influ- ence on the receiver. on the rx path, a hp filter must be used in order to reduce the echo signal level and to avoid saturation of the input stage of the receiver. the pots filter is used in both directions to re- duce crosstalk between adsl signals and pots speech and signalling. low pass pots filter can be very simple for lite - adsl application lp138khz sc2 xtral driver rxp(0:1) rxn(0:1) txp txn d98tl357mod 35.328mhz pots lp pots filter line zo=100 hp pots filter 2:1 12.5 12.5 lpf grx rr 2r 2r gtx line driver hpf lna 0..31db -15..0db pd lp 1.1mhz hc2 12-bit a/d converter 12-bit d/a converter master clock 35.328mhz nibbles 17.664mhz word 8.832/4.416mhz rxn 8.832ms/s 4.416ms/s ctrlin ltnt=1 resetn txn 8.832ms/s 4.416ms/s 4 4 rxt1 rxt2 to stlc60135 figure 4. atu-c end block diagram. lp 1.1mhz hc2 vcodac xtal driver rxp(0:1) rxn(0:1) txp txn d98tl358mod 35.328 mhz vcxout pots lp potsfilter line zo=100 hp pots filter 1:1 50 50 hpf grx rr 2r 2r gtx li ne driver lpf lna 0. .31db -15..0db pd lp 138khz sc2 12- bit a/d converter 12-bit d/a converter master clock 35.328mhz nibbles 17.664mhz word 8.832/4.416mhz rxn 8.832ms/s 4.416ms/s ctrlin ltnt=0 resetn txn 8.832ms/s 4.416ms/s 4 4 rxt1 rxt2 to stlc60135 figure 5. atu-r end block diagram. STLC60134S 6/22
rx path speech filter an external bi-directional lc filter for up and downstream pots service splits the speech sig- nal from the adsl signal to the pots circuits on atu-c. the adsl analog front end integrated circuit does not contain any circuitry for the pots serv- ice but it guarantees that bandwidth is not dis- turbed by spurious signals from the adsl-spec- trum. channel filters the external analog circuits provide partial echo cancellation by an analog filtering of the receive signal for both atu-r (reception of downstream channel) and atu-c (reception of upstream channel). this is feasible because the upstream and the downstream data can be modulated on separate carriers (fdm). line noise model the power spectral density of the crosstalk noise sources as described in ansi document is given in the figure below (no hdb3 interferer signals). also given in dotted line, is the noise model used in this document to specify the sensivity require- ments which are stronger than the original ones. signal to noise performance rx- path sensitivity at maximum gain the rx path sensitivity at the maximal rx-agc of the atu-r receiver is defined at -140dbm/hz (for 100 w ref) on the line. this figure corresponds to the equivalent input noise of 31nvhz -1/2 seen on the line. the sensitivity at the maximal rx - gain of the atu-c receiver is defined at -130dbm/hz (for 100 w ref) on the line. the figure corresponds to the equivalent input noise of 100nvhz -1/2 seen on the line. both noise figures include the noise of the hybrid. it is the equivalent average thermal noise over the frequency band of interest. the maximum noise density within the pass band can exceed the average value as follows: atu-r rx path (max agc setting): <100nvhz -1/2 @ 138khz <31nvhz -1/2 for 250khz < f atu-c rx path (max agc setting): <100nvhz -1/2 for 34.5khz < f <138khz rx-path noise at minimum gain at the minimum agc the total average thermal noise of the analog rx-path at the adc input should be lower than the adc quantisation noise. the maximum noise density within the pass band can exceed the average value as follows: atu-r rx path (min agc setting): <500nvhz -1/2 @ 138khz < f atu-c rx path (min agc setting): <1.5 m vhz -1/2 @ 34.5khz < f < 138khz these noise specifications correspond with 10bit resolution of the complete rx-path. table 4. rx common-mode voltage description value/unit common mode signal v cm at rxin1 and rxin2: 1.6v < v cm <1.7v agc of rx path the agc gain in the rx-path is controlled through a 5-bits digital code. four inputs are provided for rx input and the se- lection is made with the rxmux bits of the ctrlin interface. this can be used to make lower gain paths in case of high input signal. table 5. agc characteristics. description value/unit input referred noise (max. gain) 20nvhz -1/2 max. input level 1vpd max. output level 1vpd gain range 0 to 31db with step = 1db gain and step accuracy 0.3db rx filters the combination of the external filter (an lc lad- der filter typically) with the integrated lowpass fil- ter must provide: - echo reduction to improve dynamic range - dmt sidelobe and out of band (anti-aliasing) attenuation. - anti alias filter (60db rejection @ image freq.) 79.5 138 250 795 khz d98tl359 -140 -130 -120 -110 -100 dbm/hz figure 6. crosstalk psd. STLC60134S 7/22
atu-r rx filters the integrated filter have the following characteristics: table 6. integrated hc filter characteristics description value/unit input referred noise 100nvhz -1/2 max. input level 1vpd max. output level 1vpd type 3rd order butterworth frequency band 1.104mhz (0%setting, see below) frequency tuning -43.75% -> +0% max. in-band ripple 1db matlab model default cut off frequency @ -3db actual cut off @ -3db hc freq. selection register [b, a] = butter (3, w0, 's') f0 = 1560khz w0 = 2 * pi * f0/((20 + n)/16) n = -4,..,3 see (afe settings ,table 22) table 7. phase characteristic description value/unit total rx filter group delay < 50 m s @ 138khz < f < 1.104mhz total rx filter group delay distortion < 15 m s @ 138khz < f < 1.104mhz note: the total atu_r rx path (including adc) group delay distortion is 16 m s (i.e. = 15 m s+1 m s of adc) atu-c rx filter this filter is the same as the one used for atu-r tx. linearity of rx linearity of the rx analog path is defined by the im3 product of two sinusoidal signals with frequencies f1 and f2 and each with 0.5vpd amplitude (total 1vpd) at the output of the rx - agc amplifier (i.e: be- fore the adc) for the case of minimal agc setting. the following tables 8 and 9 list the rx path intermodulation distortion (as s/im3 ratio) in downstream and upstream bandwidth. amplitutde 0db +/-1db 5db 36db 50db 30 1104 2208 7728 16560 khz d98tl360 figure 7. hc filter mask for atu-r rx and atu-c tx table 8. linearity of atu-r rx f1 (0.5vpd) f2 (0.5vpd) 300khz 200khz 500khz 400khz 700khz 600khz s/im3 (agc = 0db) 59.5db @ 100khz 53.5db @ 400khz 43.5db @ 700khz 42.5db @ 800khz 59.5db @ 300khz 48.0db @ 600khz 48.0db @ 500khz 42.5db @ 800khz STLC60134S 8/22
table 9. linearity of atu-c rx f1 (0.5vpd) f2 (0.5vpd) s/im3 (agc = 20 db) 2f2 - f1 2f1 - f2 80khz 70khz 56.5db @ 60khz 56.5db @ 90khz table 10. rx filter to a/d interface rx filter to a/d maximal level: 1vpd = full scale of a/d table 11. a/d convertors (a pipeline architecture is used for a/d convertors). numbers of bits: 12bits minimum resolution of the a/d convertor 11bits linearity error of the a/d convertor <1lsb (out of 12bits) full scale input range: 1 vpdif 5% sampling rate: 8.832mhz (or 4.416mhz in osr = 2 mode) maximum attenuation at 1.1mhz: <0.5db without in-band ripple maximum group delay: <3 m s maximum group delay distortion: <1 m s power supply rejection the noise on the power supplies for the rx path must be lower than the following: <50mvrms in band white noise for any avdd. in this case, psr (power supply rejection) of STLC60134S rx path is lower than -43db. tx path transmitter spectral response the two figures below show the ansi spectral response mask for atu-c and atu-r transmitters dbm/hz -40 +/-3db 24db 50db 30 1104 2208 11040 khz d98tl361 -64 -90 figure 8. atu-c tx spectral response mask dbm/hz -40 +/-3db 24db 48db 30 138 181 224 khz d98tl362 -64 -88 figure 9. atu-r tx spectral response mask STLC60134S 9/22
table 12. agc of tx path (from filter output to txp and txn). output noise 25mvhz -1/2 input level (nominal) 1vpd output level nominal, full-scale 1.5vpd maximum output load > 500 w ; <10pf agc range: -15db...db agc step: 1db gain and step accuracy 0.3db minimum code (0000) stands for agc = -15db and maximum (1111 - msb left) for agc = 0db (see tx setting, table22). tx pre-driver capability the pre-driver drives an external line power amplifier which transmits the required power to the line. table 13. tx pre-driver tx drive level to the external line driver for max. agc setting 1.5 vpdif external line driver input impedance: resistive capacitive > 500 w < 30pf pre-driver characteristics: closed loop gain: -15db...0db with step = 1db ooutput impedance: output offset voltage (0db) < 10mv input noise voltage (0db) < 20nvhz -1/2 @ f > 250k w < 50nvhz -1/2 @ 34.5k < f <138k w output common mode voltage: 1.6v < vcm < 1.7v tx filter the tx filters act not only to suppress the dmt sidebands but also as smoothing filters on the d/a con- vertor's output to suppress the image spectrum. for this reason they must be realized in a continuous time approach. atu-r tx filter the purpose of this filter is to remove out-of-band noise of the atu-r tx path echoed to the atu-r rx path. in order to meet the transmitter spectral response, an additional filtering must be (digitally) per- formed. the integrated filter has the following characteristics: table 14. integrated sc filter characteristics description value/unit input referred noise 100nvhz -1/2 max. input level 1vpd max. output level 1vpd type 4th order chebytchef frequency band 138khz (0% setting see below) frequency tuning -25% -> +25% max. in-band ripple 1db matlab model default cut-off frequency @ -3db actual cut-off @ -3db sc freq. selection register [b,a] = cheby1 (4,0.5,w0,'s') {ripple = 0.5} f0 = 151.8khz w0 = 2*pi*f0/((17+n)/16) n = -4,..,3 see (afe settings, table 22) STLC60134S 10/22
table 15. phase characteristics description value/unit total tx filter group delay <50 m s @ 34.5khz < f < 138khz total tx filter group delay distortion <20 m s @ 34.5khz < f < 138khz note: the total atu-r tx path (including dac) group delay distortion is 16 m s (i.e. = 15 m s+1 m s of dac) amplitutde 0db +/-1db 20db 30 138 250 khz d98tl363 figure 10. sc filter mask for atu-crx and atu-r tx table 16. d/a convertor (a current steering architecture is used). description value/unit numbers of bits: 12bits minimum resolution of the d/a convertors 11bits linearity error of the a/d convertor <1lsb (out of 12bits) full scale input range: 1 vpdif 5% sampling rate: 8.832mhz (or 4.416mhz in compatible mode) maximum group delay: <3 m s maximum group delay distortion: <1 m s linearity of atu-c tx linearity of the tx is defined by the im3 product of two sinusoidal signals with frequencies f1 and f2 and each with 0.5vpd amplitude (total 1vpd) at the output of the pre-driver for the case of a total agc = 0db. table 17. linearity of atu-c tx f1 (0.5vpd) f2 (0.5vpd) 300khz 200khz 500khz 400khz 700khz 600khz s/im3 (agc = 0db) 59.5db @ 100khz 53.5db @ 400khz 43.5db @ 700khz 42.5db @ 800khz 59.5db @ 300khz 48.0db @ 600khz 48.0db @ 500khz 42.5db @ 800khz STLC60134S 11/22
linearity of atu-r tx table 18. linearity of atu-r tx f1 (0.5vpd) f2 (0.5vpd) s/im3 (agc = 0 db) 80khz 70khz 59.5db (@ 60khz, 90khz) table 19. atu-c tx idle channel noise for max agc setting (0db) in-band noise out-of-band noise 500nvhz -1/2 500nvhz -1/2 @ 138khz -1.104mhz @ 34.5khz -138khz for min agc setting (=-15db) in-band noise 80nvhz -1/2 @ 138khz -1.104mhz tx idle channel noise atu-c tx idle channel noise the idle channel noise specifications correspond with 11bit resolution of the complete tx-path. atu-c tx idle channel output noise on tx. atu-r tx idle channel noise atu-r tx idle channel output noise on txp, txn table 20. atu-r tx idle channel noise for max agc setting (0db) in-band noise out-of-band noise 1.6 m vhz -1/2 1.6 m vhz -1/2 150nvhz -1/2 @ 34.5khz -138khz @ 138khz @ 250khz -1.104mhz for min agc setting (=-15db) in-band noise 500nvhz -1/2 @ 34khz -138khz power supply rejection the noise on the power supplies for the tx-path must be lower than the following: < 50mvrms in-band white noise for avdd. < 15mvrms in-band white noise for pre-driver avdd. vcxo a voltage controlled crystal oscillator driver is integrated in STLC60134S. the nominal frequency is 35.328mhz. the quartz crystal is connected between the pins xtali and xtalo. the principle of the vcxo control is shown in figure 11. the information coming from the digital processor via the ctrlin path is used to drive an 8-bit dac which generates a control current. this current is externally converted and filtered to generate the re- quired control voltage (range:-15v to 0.5v) for the varicap. the vcxo circuit characteristics are given in table 21. STLC60134S 12/22
table 21. vcxo circuit characteristics symbol parameter min. nominal max. note f abs absolute frequency accuracy -15ppm 35.328mhz +15ppm f range frequency tuning range 50ppm i o vcxo output current 100 m a rref = 16.5k w avdd = 3.3v i i reference input current 100 m a 1ma avdd = 3.3v n.b: frequency tuning range is proportional to the crystal dynamic capacitance c m . dac c t r t agnd xtalo xtali c p vcxout ivco r ref i i i o =i i avdd avdd/22 avdd/2 filtered vcxo (se e ctrlin table) vcocx avdd 1m w clk35 30% c s -15v ctrlin 8 bits d98tl364mod figure 11. principle of vcxo control the tuning must be monotonic with 8-bit resolution with the worst-case tuning step of <2ppm/lsb (8-bit). the time constant of the tuning must be variable from 5s to 10s through an external capacitor c s (r = 1m w 30%). this determines the speed of the vcxo in normal operation (slow speed in oshow timeo) with filtered vcxo. for faster tracking, the previous filter is not used and the speed depends on ctrt. STLC60134S 13/22
digital interface control interface the digital setting codes for the STLC60134S configuration are sent over a serial line (ctrlin) using the word clock (clwd). the data burst is composed of 16 bits from which the first bit is used as start bit ('0'), the three lsbs be- ing used to identify the data contained in the 12 remaining bits. test related data are overruled by the normal settings if the test pin is low. table 22. control interface bit mapping m s b l s b rx settings b 1 5 b 1 4 b 1 3 b 1 2 b 1 1 b 1 0 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 x 0 0 0 external gain control gc1 (init = 0) 0 x 0 0 0 external gain control gc0 (init = 0) 0 0 0 0 0 rx input selected = rxin0, rxip0 (init) 0 1 0 0 0 rx input selected = rxin1, rxip1 0 00000 000agcrx gain setting 0db (init) 0 00001 000agcrx gain setting 1db 0 x x x x x 0 0 0 agc rx gain setting xdb 0 11111 000agcrx gain setting 31db 0 0 0 0 0 0 normal mode filter selection see ltnt pin (init) 0 0 1 0 0 0 in atu-c conf, force hc2 for rx path, tx grounded 0 1 0 0 0 0 in atu-c conf, force hc1 for rx path 0 1 1 0 0 0 normal mode filter selection see ltnt pin b 1 5 b 1 4 b 1 3 b 1 2 b 1 1 b 1 0 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 tx settings 0 0 0 0 0 0 0 1 transmit tx - agc setting -15db (init) 0 0 0 0 1 0 0 1 transmit tx - agc setting -14db 0 x x x x 0 0 1 transmit tx - agc setting (x - 15) db 0 1 1 1 1 0 0 1 transmit tx - agc setting 0db 0 0000 001not used (init) 0 0000 001not used (init) 0 0000 001not used (init) 0 0000 001not used (init) 0 x x x 0 0 1 general purpose output (gpo) setting (init = 000) b 1 5 b 1 4 b 1 3 b 1 2 b 1 1 b 1 0 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 afe settings 0 0 0 1 0 normal mode (digital path) (init) 0 1 0 1 0 digital loopback (digital tx to digital rx - dac not used) 0 0 0 1 0 normal mode (analog path) 0 1 0 1 0 analog loopback (rxi to txi - adc not used) 1) (init) 0 0 0 1 0 vco dac disabled 0 1 0 1 0 vco dac enabled (init) 0 0 0 1 0 hc filter enabled (init) 0 1 0 1 0 hc filter enabled 1) after initialization, this bit has to be cleared (0) to make the device properly operate. STLC60134S 14/22
b 1 5 b 1 4 b 1 3 b 1 2 b 1 1 b 1 0 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 afe settings 0 0 0 1 0 osr set to 4 (init) 0 1 0 1 0 osr set to 2 0 1 1 1 0 1 0 sc freq. selection: fc = 138khz (init) (*) 0 0 1 1 0 1 0 sc freq. selection: fc ~ 110khz (*) 0 1 0 1 0 1 0 sc freq. selection: fc ~ 170khz (*) 0 1 0 0 0 1 0 hc freq. selection: fc = 1.104mhz (init) (*) 0 0 1 1 0 1 0 hc freq. selection: fc ~ 768khz (*) 0 0 0 1 0 vcxo output not filtered (oshow-timeo) (init) 0 1 0 1 0 vcxo output filtered b 1 5 b 1 4 b 1 3 b 1 2 b 1 1 b 1 0 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 vco dac value settings 000000000 011vcodac current value @ minimum 0 x x x x x x x x 0 1 1 vco dac current value @ x 011111111 011vcodac current value @ maximum b 1 5 b 1 4 b 1 3 b 1 2 b 1 1 b 1 0 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 power down analog block settings 0 0 1 0 0 txd active (init) 0 1 1 0 0 txd in powerdown 0 0 1 0 0 n.u. (init) 0 1 1 0 0 n.u. 0 0 1 0 0 adc active (init) 0 1 1 0 0 adc in powerdown 0 0 1 0 0 hfc2 active (init) 0 1 1 0 0 hfc2 in powerdown 0 0 1 0 0 hfc1 active (init) 0 1 1 0 0 hfc1 in powerdown 0 0 1 0 0 scf2 active (init) 0 1 1 0 0 scf2 in powerdown 0 0 1 0 0 scf1 active (init) 0 1 1 0 0 scf1 in powerdown 0 0 1 0 0 lna active (init) 0 1 1 0 0 lna in powerdown 0 0 1 0 0 dac active (init) 0 1 1 0 0 dac in powerdown 0 0 1 0 0 dace active (init) 0 1 1 0 0 dace in powerdown 0 0 1 0 0 vcodac active (init) 0 1 1 0 0 vcodac in powerdown 0 0 1 0 0 xtal active (init) 0 1 1 0 0 xtal in powerdown b 1 5 b 1 4 b 1 3 b 1 2 b 1 1 b 1 0 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 reserved 0 x x x x x x x x x x x x 1 0 1 reserved 0 x x x x x x x x x x x x 1 1 0 reserved 0 x x x x x x x x x x x x 1 1 1 reserved (*) for each filter, 8 possible frequency values (see table 6 and table 14). notation is 2's complement range from -4 = 100b +3 = 011b. fc is the frequency band (-1db) table 22. control interface bit mapping (continued) STLC60134S 15/22
control interface timing the word clock (clwd) is used to sample at negative going edge the control information. the start bit b15 is transmitted first followed by bits b[14:0] and at least 16 stop bits need to be provided to validate the data. ctrlin clwd start bit data id. >=16 stop bits=high d98tl365 figure 12. control interface. data set-up and hold time versus falling edge clwd must be greater than 10nsec. receive / transmit interface receive / transmit protocol the digital interface is based on 4 x 8.832mhz (35.328mhz) data lines in the following manner: if osr = 2 (osr bit set to 1) is selected, clknib is used as nibble clock (17.664mhz, disabled in normal mode), and all the rxi, txi, clkwd periods are twice as long as in normal mode. this ensures a compati- bility with lower speed products. tx signal dynamic the dynamic of data signal for both tx dacs is 12 bits extracted from the available signed 16 bit repre- sentationcoming from the digital processor. the maximal positive number is 2 14 -1, the most negative number is -2 14 , the 3 lsbs are filled with '0'. any signal exceeding these limits is clamped to the maximum value. n3 n2 n1 n0 sign sign d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 n.u. n.u. n.u. the two sign bits must be identical. table 24. tx bit map table 23. bit map/nibble n0 n1 n2 n3 txd0 not used data bit 1 data bit 5 data bit 9 txd1 not used data bit 2 data bit 6 data bit 10 txd2 not used data bit 3 data bit 7 data sign txd3 d0 = data bit 0 (lsb) data bit 4 data bit 8 data sign STLC60134S 16/22
rx signal dynamic the dynamic of the signal from the adc is limited to 13bits. those bits are converted to a signed (2's complement) representation with a maximal positive number of 2 14 -1 and a most negative number -2 14 . the 2 lsbs are filled with '0'. n3 n2 n1 n0 sign sign d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 the two sign bits must be identical. table 26. rx bit map table 25. bit map/nibble n0 n1 n2 n3 rxd0 0 data bit 2 data bit 6 data bit 10 rxd1 0 data bit 3 data bit 7 data bit 11 rxd2 d0 = data bit 0 (lsb) data bit 4 data bit 8 data sign rxd3 data bit 1 data bit 5 data bit 9 data sign n0 n1 n2 n3 osr=4 clkm 35.328mhz clwd 8.832mhz txdx/rxdx n0 n1 n2 n3 osr=2 clknib 17.664mhz clwd 4.416mhz txdx/rxdx d98tl366 figure 13. tx/ rx digital interface timing receive / transmit interface timing the interface is a triple (rx, tx) nibble - serial interface running at 8.8mhz sampling (normal mode). the data are represented in 16bits format, and transferred in groups of 4 bits (nibbles). the lsbs are transferred first. the STLC60134S generates a nibble clock (clkm master clock in normal mode, clknib in osr = 2 mode) and word signals shared by the three interfaces. data is transmitted on the rising edge of the master clock (clkm/clknib) and sampled on the falling edge of clkm/clknib. this holds for the data stream from STLC60134S and from the digital proces- sor. data, clwd setup and hold times are 5ns with reference to the falling edge of clkm/clknib. (not floating). STLC60134S 17/22
data is transmitted on the rising edge of the master clock (clkm/clknib) and sampled on the low going edge of clkm/clknib. this holds for the data stream from STLC60134S and from the digital processor. data,clwd setup and hold times are 5ns with reference to the falling edgeof clkm/clknib. (not floating). power down when pin pdown = o1o, the chip is set in power down mode. as the pdown signal is synchronously sam- pled, minimum duration is 2 periods of the 35mhz clock. in this mode all analog functional blocks are deactivated except: preamplifiers (tx), clock circuits for output clock clkm. p down will not affect the digi- tal part of the chip. anyway, after a pdown transition, the digital part status, is updated after 3 clock peri- ods (worst case) the chip is activated when p down = o0o. in power down mode the following conditions hold: - output voltages at txp/txn = agnd - preamplifier is on with maximum gain setting (0db), (digitalgain setting coefficients are overruled) - the xtal outputclock on pin clkm keepsrunning. - all digital setting are retained. - digital output on pins rxdx don't care (not floating). in power-down mode the power consumption is 100mw. following external conditions are added: - clock pin clw is running. - ctrlin signals can still be allowed. - agnd remains at avdd/2 (circuit is powered up) - input signal at txdx inputs are not strobed. the pdown signal controls asynchronously the power-down of each analog module: - after a few m s the analog channel is functional - after about 100ms the analog channel delivers full performance reset function the reset function is implied when the resetn pin is at a low voltage input level. in this condition, the reset function can be easily used for power up reset conditions. detailed description during reset: (reset is asynchronous, tenths of ns are enough to put the ic in reset) all clock outputs are deactivatedand put to logical o1o (except for the xtal and master clock clkm) after reset: (4 clock periods after reset transition, as worst case) - osr = 4 - all analog gains (rx, tx) are set to minimum value - nominal filter frequency bands(138khz, 1.104hz) - lna input = o11o (max. attenuation) - vco dac disabled - depending of the ltnt pin value the following configuration is chosen: '0' (atu-r) rx: lna -> hc2 -> adc tx: dac -> sc2 -> tx '1' (atu-c) rx: lna -> sc2 -> adc tx: dac -> hc2 -> tx STLC60134S 18/22
electrical ratings and characteristics table 27. absolute maximum ratings symbol parameter min max unit v dd any vdd supply voltage, related to substrate - 0.5 5 v v in voltage at any input pin -0.5 v dd +0.5 v t stg storage temperature -40 125 c t l lead temperature (10 second soldering) 300 c i lu latch - up current @80 c 100 ma i avdd analog supply current @ 3.6v - normal operation 165 ma i avdd analog supply current @ 3.6v - power down 30 ma i dvdd analog supply current @ 3.6v - normal operation 56 ma i dvdd analog supply current @ 3.6v - power down 50 ma table 28. thermal data symbol parameter value unit r th j-amb thermal and junction ambient 50 c/w table 29. operating conditions (unless specified, the characteristic limits of 'static characteristics' in this document apply over an t op = -40 to 80 c; vdd within the range 3 to 3.6v ref. to substrate. symbol parameter min max unit avdd avdd supply voltage, related to substrate 3.0 3.6 v dvdd dvdd supply voltage, related to substrate 2.7 3.6 v v in /v out voltage at any input and output pin 0 v dd v p d power dissipation 0.4 0.6 w t amb ambient temperature -40 80 c t j junction temperature -40 110 c digital outputs are placed in don't care condition (non-floating). n.b. if a xtal oscillator is used, the reset must be released at last 10 m s after power-on, to ensure a correct duty cycle for the clk35 clock signal. STLC60134S 19/22
static characteristics table 30. digital inputs schmitt-trigger inputs: txi, ctrlin, pdown, ltnt, resetn, test symbol parameter test condition min. typ. max. unit v il low level input voltage 0.3 ? dvdd v v ih high level input voltage 0.7 ? dvdd v v h hysteresis 1.0 1.3 v c imp input capacitance 3 pf table 31. digital outputs hard driven outputs: rxi symbol parameter test condition min. typ. max. unit v ol low level output voltage i ou t = -4ma 0.15 ? dvdd v v oh high level output voltage i ou t = 4ma 0.85 ? dvdd v c load load capacitance 30 pf clock driver output: clkm, clnib, clkwd symbol parameter test condition min. typ. max. unit v ol low level output voltage i ou t = -4ma 0.15 ? dvdd v v oh high level output voltage i ou t = 4ma 0.85 ? dvdd v c load load capacitance 30 pf dc duty cycle 45 55 % STLC60134S 20/22
tqfp64 dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.18 0.23 0.28 0.007 0.009 0.011 c 0.12 0.16 0.20 0.0047 0.0063 0.0079 d 12.00 0.472 d1 10.00 0.394 d3 7.50 0.295 e 0.50 0.0197 e 12.00 0.472 e1 10.00 0.394 e3 7.50 0.295 l 0.40 0.60 0.75 0.0157 0.0236 0.0295 l1 1.00 0.0393 k 0 (min.), 7 (max.) a a2 a1 b c 16 17 32 33 48 49 64 e3 d3 e1 e d1 d e 1 k b tqfp64 l l1 seating plane 0.10mm outline and mechanical data STLC60134S 21/22
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a trademark of stmicroelectronics tosca ? is trademark of stmicroelectronics ? 1999 stmicroelectronics and alcatel alsthom, paris printed in italy all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com STLC60134S 22/22

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